The present invention relates to a semiconductor device, and particularly relates to a structure of a plurality of leads electrically connected to a semiconductor element.
In a tendency of increase of the number of leads of a semiconductor device with rapid progress in moving forward with high integration and multifunction of a semiconductor device, along with reducing a substrate for mounting the semiconductor device, miniaturizing a package of the semiconductor device is demanded. Basically, reduction of an arrangement interval between each lead, reduction of a width of each lead and the like have been carried out. However, these types of reduction reach a limit in view of precision and strength of the leads. Thus, various methods for miniaturizing a package through change of a structure of the leads have been proposed. An example (Japanese Patent Unexamined Publication No. Hei. 2-26059) of such methods is shown in FIG. 5.
In FIG. 5, a plurality of leads 1 are arranged up and down, lower stage leads 1a and upper stage leads 1b are overlapped with each other, and these are bonded to each other by an electrically insulative adhesive 2 such as an epoxy resin shown by hatching in FIG. 5, so that two-stage structure is formed. End portions of the respective lower stage leads 1a are positioned nearer a die pad 6 than end portions of the respective upper stage leads 1b. The end portions of the respective leads 1a and 1b are connected to a semiconductor element 4 on the die pad 6 through wires 5a and 5b.
The leads are arranged up and down in two stages, so that a size in lead arrangement direction X can be reduced by about 1/2 as compared with an arrangement in which leads are arranged in the same plane.
Japanese Patent Unexamined Publication No. Sho. 60-107848 proposes a semiconductor device in which leads inside and outside a package are arranged in two stages in a staggered manner so that the package is made compact.
However, according to the package disclosed in Japanese Patent Unexamined Publication No. Hei. 2-26059, (1) the lower stage leads and the upper stage leads are overlapped with each other, so that the respective wires 5a and 5b are arranged in the substantially same vertical plane, and (2) the respective wires 5a and 5b are bonded in a state that the wires have a some degree of sag so that the wires are not broken even if a contracting force at hardening of the package 3, which is formed by hardening the epoxy resin and the like, is applied to the wires. Accordingly, when wire bonding is carried out, or when an epoxy resin as a package agent is injected, there is strong possibility that the upper stage wire 5b is lowered to contact the lower stage wire 5a. Thus, a rate of occurrence of inferior goods due to a short increases to cause reduction of a yield.
As described above, when the structure of leads are changed from a plane structure to an up and down two-stage arrangement structure in order to miniaturize a package, there arises such problems that wire bonding for connecting each lead to a semiconductor element is made complicated, and wires contact with each other.
According to the package disclosed in Japanese Patent Unexamined Publication No. Sho. 60-107848, the end portions of inner leads are arranged in the same plane around a die pad, so that the interval between leads can not be narrowed very much in order to assure insulation between the respective inner leads. Further, the width of the end portion of the inner lead must have a some degree of largeness in order to facilitate the wire bonding to the lead end portion. Accordingly, there is a problem that the number of the inner leads arranged around the die pad is restricted.